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DS28CZ04: 4Kb I2C/SMBus EEPROM with Nonvolatile PIO
Table 1A. Write Access
WRITING WHILE DEVICE IS NOT BUSY
PIO Mode
Multi-
Address
Single-
Address
Starting Address
Device address = A0h,
any 16-byte block except
70h to 7Fh ;
Device address = A2h,
any 16-byte block except
60h to 6Fh, F0h to FFh
(normal EEPROM)
Device address = A0h,
memory address from
70h to 77h (short
EEPROM)
Device address = A2h,
memory address from
60h to 6Fh (special
EEPROM)
Device address = A2h,
memory address from
F0h to FFh (reserved)
Device address = A0h,
memory address from
78h to 7Bh (SRAM write)
Device address = A0h,
memory address from
7Ch to 7Fh (PIO direct)
Device address = A0h ,
memory address from
78h to 7Fh excluding
7Ch (SRAM write)
Device address = A0h ,
memory address = 7Ch
(PIO direct)
All other cases
SMBus or I2C Bus Mode
If WP pin is tied to GND : Slave address is acknowledged;
memory address is acknowledged, data is acknowledged;
write pointer increments and wraps around from end of block to
beginning of block, read pointer = write pointer +1.
If WP pin is tied to V CC : data is not acknowledged, no EEPROM
write cycle takes place; everything else remains the same.
Same as “normal EEPROM” except that write pointer wraps
around from 77h to 70h .
SFF mode off : same as “normal EEPROM”.
SFF mode on : data for address 6Eh is not acknowledged;
everything else is the same as with “normal EEPROM”.
Same as “normal EEPROM” except that data is not
acknowledged.
Slave address is acknowledged; memory address is acknowl-
edged, data for address 78h and 79h is not acknowledged; write
pointer increments and wraps around from 7Fh to 7Ah , read
pointer = write pointer +1.
Slave address is acknowledged; memory address is
acknowledged, data is acknowledged;
write pointer increments and wraps around from 7Fh to 7Ch ,
read pointer = write pointer +1.
Slave address is acknowledged; memory address is
acknowledged, data for addresses 7Dh to 7Fh and 78h to 79h is
not acknowledged; write pointer increments and wraps around
from 7Fh to 7Ah , read pointer = write pointer +1.
Slave address is acknowledged; memory address is
acknowledged, data is acknowledged;
write pointer stays at 7Ch ; read pointer stays at 7Ch .
Same as in PIO Multi-Address Mode.
Busy Polling
While busy, the behavior of the DS28CZ04 depends on the communication mode, which is selected through the
CM bit of the Direction and Control/Status Register (Device Address A0h) at address 7Ah. Tables 1B and 2B show
details. The PIO address mode does not affect the device behavior when busy.
In I2C bus mode , when busy the DS28CZ04 does not acknowledge its slave address until the write cycle is
completed. The master can access the device by transmitting the Slave Address/Direction Byte and testing
whether the address is acknowledged. As soon as the DS28CZ04 acknowledges, the master knows that the device
is ready for further activities.
In SMBus mode , the DS28CZ04 always acknowledges its slave address. The only way for the master to detect the
completion of the write cycle is through the BUSY bit in the Direction and Control/Status Register (Device Address
A0h) at. To get to this bit the master must first address the DS28CZ04 in write access mode, Device Address A0h,
and set the memory address to 7Ah (see Table 1B). Now the master can address the DS28CZ04 in read access
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